This invention relates to a semiconductor memory device and to a method of manufacturing the same. More particularly, the invention relates to a semiconductor memory device ideal for use in a semiconductor memory comprising an SRAM (Static Random-Access Memory), and to a method of manufacturing the device.
Memories well-known in the art and typified by LSI circuits (Large-Scale Integrated Circuits) are classified into SRAMs and DRAMs (Dynamic Random-Access Memories). Almost all of these memories are constituted by MOS (Metal-Oxide Semiconductor) transistors which excel in terms of degree of integration. Further, since SRAMs are advantageous in that they have a higher operating speed than DRAMs, they find wide application for use particularly in memories such as cache memories requiring a high operating speed.
An SRAM basically is constituted by a flip-flop circuit. The flip-flop circuit employs a pair of MOS transistors for drive, in which the input and output electrodes of the transistors are connected together and a load element (pull-up element) is connected to each output electrode. SRAMs are classified broadly into the CMOS (Complementary Metal-Oxide Semiconductor) type, which uses a MOS transistor as the load element of the flip-flop circuit, and the high-resistance load type, which uses a high-resistance thin film such as a polycrystalline silicon as the load element. By connecting MOS transistors for address selection to the pair of output electrodes, one memory cell is constructed.
In the CMOS-type SRAM, one memory cell is composed of six MOS transistors. This is disadvantageous in that the area occupied by one memory cell in the semiconductor substrate is large. By contrast, the high-resistance-type SRAM is such that one memory cell is composed of only four MOS transistors, and the high-resistance thin film can be formed at a position above the MOS transistors. This makes it possible to reduce the cell area. However, since high-resistance load elements comprising polysilicon or the like must be formed in a stacked structure in the limited space available in the memory cell, a complicated memory cell structure is unavoidable. This leads to an increase in the number of manufacturing steps.
Important factors in the semiconductor memory devices described above are reducing cell size to raise the degree of integration, simplifying the manufacturing process to reduce the labor involved in manufacture, and assuring stability of operation. These challenges give rise to the problems described below.
Problems involving a reduction in cell size will be discussed first. A semiconductor memory device described below is disclosed in applications filed earlier by the present inventor (Japanese Patent Application Nos. 10-109261 and 10-346149 claiming priority of No. 10-109261, now JP-P2000-12705A; the entire disclosures thereof being incorporated herein by reference thereto) and its manufacture employs a method of realizing a reduction in the cell area of the device. The semiconductor memory device includes a pair of address-selecting MOS transistors comprising p-type MOS transistors and a pair of driving MOS transistors comprising n-type MOS transistors formed on a p-type semiconductor substrate. Instead of provision of high-resistance load elements, a threshold-voltage-value adjustment layer is formed in channel regions of the pair of driving MOS transistors.
A threshold-voltage value Vthn of the pair of driving MOS transistors comprising the n-type MOS transistors is set so that the absolute value thereof will be larger than a threshold-voltage value Vthp of the pair of address-selecting MOS transistors comprising the p-type MOS transistors (|Vthn|xe2x89xa7|Vthp|). This is accomplished by forming the threshold-voltage-value adjustment layer in the channel regions of these MOS transistors by adding on a series of new steps (a PR step and an ion-injection step).
The reason for thus setting the threshold voltage value of the MOS transistors is to arrange it so that data that has been stored in the memory cell can be retained without using a third potential, namely a potential other than the power-source potential and ground potential. That is, by satisfying the above-mentioned relationship, leakage current ILp of the address-selecting MOS transistors can be made larger than leakage current ILn of the driving MOS transistors (ILpxe2x89xa7ILn).
As a result, when the power-source potential is applied to the gate electrodes of the address-selecting MOS transistors during standby, loss of electric charge is compensated for by passing a sub-threshold current through these transistors, whereby an output node of the driving transistors can be maintained at the power-source potential. Thus, resultant compensation for loss of charge in the memory cell makes it possible to retain data.
On the other hand, it is known that when Vthn is set too high in comparison with Vthp, cell stability (static noise margin) suffers, as described in the specification of Japanese Patent Application No. 10-346149).
Thus, if a semiconductor memory device in accordance with the earlier applications of the present inventor is used, a reduction in cell size can be achieved. However, because stored data is retained while maintaining the stability of the memory cell by the threshold-voltage-value adjustment layer formed in the channel region of the driving MOS transistors, it is necessary to control the impurity concentration of the channel region of each of the driving MOS transistors. The problem is that manufacture of this device is accompanied by difficulties. This represents a first problem encountered in the course of the investigations toward the present invention.
If alpha rays impinge upon an integrated semiconductor memory device, electron-hole pairs are produced within the MOS transistors, as shown in FIG. 16, and a soft error in which the electric charge invites erroneous circuit operation occurs. A method of preventing such soft error is available and involves forming a transistor having a triple-well structure in which a p-well region is surrounded by an n-well region. In accordance with this method, it is possible to suppress electric charge that flows into the p-well region. On the other hand, the new series of steps (the PR step and ion-injection step) for forming the deep n well region must be added on. This results in a greater number of steps. This a second problem encountered.
Accordingly, an object of the present invention is to provide a semiconductor memory device, and a method of manufacturing the same, in which a deep n-well structure is realized through a single PR step and a threshold-voltage value of n-type transistors within the memory cell is made higher than a threshold-value voltage of n-type transistors in the peripheral circuit.
It is another object of the present invention to improve the operating stability of the semiconductor memory device and effectively suppressing soft error, and in which the threshold-voltage value can be control led freely in the case of a 4-transistor SRAM not having high-resistance load elements.
Further objects of the present invention will become apparent in the entire disclosure.
According to a first aspect of the present invention, the foregoing object is attained by providing a loadless 4-transistor SRAM in which a memory portion and a peripheral circuit portion are disposed on a semiconductor substrate of first conductivity type in which a plurality of wells have been formed, a pair of driving MOS transistors and a pair of address-selecting MOS transistors are formed in the memory portion, and a channel region of the driving MOS transistors is provided with a layer of injected (doped) impurities (impurity-doped layer) of a prescribed concentration for adjusting a threshold-voltage value, wherein a well of a second conductivity type is formed below a well of the memory portion.
According to a second aspect of the present invention, the foregoing object is attained by providing a semiconductor memory device of triple-well structure in which a memory portion and a peripheral circuit portion are disposed on a semiconductor substrate of first conductivity type in which a plurality of wells have been formed, impurity concentration of a well of the first conductivity type of the memory portion is set to be higher than impurity concentration of a well of the first conductivity type of the peripheral circuit portion, and a well of a second conductivity type is provided below a well of the memory portion, wherein the well of the second conductivity type provided below the well of the memory portion is formed so as to cover only the well of the first conductivity type of the memory portion.
According to a third aspect of the present invention, the foregoing object is attained by providing a method of manufacturing a semiconductor memory device in which impurity ions are implanted (doped) using a resist pattern of a prescribed shape, which has been formed on a semiconductor substrate, as a mask, wherein the impurity ions are implanted into the semiconductor substrate upon passing through an area of the resist pattern the thickness whereof is reduced in the direction in which the impurity ions are injected (implanted), the area of reduced effective thickness being adjacent an aperture of the resist pattern.
According to a fourth aspect of the present invention, the foregoing object is attained by providing a method of manufacturing a semiconductor memory device in which impurity ions are injected (implanted) using a resist pattern of a prescribed shape, which has been formed on a semiconductor substrate, as a mask, thereby forming a region of injected (doped) impurities having a shape substantially the same as that of an aperture of the resist pattern, wherein the shape of the region of impurities injected (doped) into the semiconductor substrate is changed by setting a direction along which the impurity ions are injected (implanted) to a predetermined angle.
In accordance with the present invention, adjustment of the impurity concentration of the p well in a memory cell and formation of a deep n well can be carried out with a single resist pattern. This makes it possible to eliminate a PR step for forming a deep n well for the purpose of preventing soft error caused by alpha rays entrant from the outside.
Further, in accordance with the present invention, the reference potential of the p-we II region of the memory cell can be controlled freely in a loadless 4-transistor SRAM. As a result, data that has been stored in the memory cell can be retained in reliable fashion.